User manual TYAN THUNDER K8HR

[. . . ] Thunder K8HR /// Version 1. 0 S3891 Copyright Copyright © TYAN Computer Corporation, 2005. No part of this manual may be reproduced or translated without prior written consent from TYAN Computer Corp. Trademark All registered and unregistered trademarks and company names contained in this manual are property of their respective owners including, but not limited to the following. AMD, Opteron, and combinations thereof are trademarks of AMD Corporation. ® Broadcom is a trademark of Broadcom Corporation and/or its subsidiaries ATI and ES1000 are trademarks of ATI Corporation Notice Information contained in this document is furnished by TYAN Computer Corporation and has been reviewed for accuracy and reliability prior to printing. [. . . ] When it is set to [Enabled], BIOS will issue a virus warning message and beep if a write to the boot sector or the partition table of the HDD is attempted. User Password: Change Supervisor Password Change User Password Disabled Boot Sector Virus Protection Enabled 68 http://www. TYAN. com 3. 9 ­ BIOS Chipset Menu This menu allows the user to customize functions of the AMD Chipsets. North Bridge configuration contains options for Memory & CPU settings. Additional configuration for the AMD8131 PCI-X Tunnel is available in the PCI-X Configuration Menu. Select a menu by highlighting it using the Arrow ( / ) keys and pressing Enter. The settings are described on the following pages. Main Advanced BIOS Setup Utility PCI/PnP Boot Security Chipset Exit NorthBridge Configuration HT2000 SystemI/O Configuration HT1000 South Bridge Configuration Options for NB. Select Screen Select Item +/- Change Option Enter Go to Sub Screen F1 General Help F10 Save and Exit ESC Exit 69 http://www. TYAN. com 3. 9. 1 ­ North Bridge Chipset Configuration Sub-Menu This menu gives options for customizing memory & Hypertransport settings. Select a menu by highlighting it using the Arrow ( / ) keys and pressing Enter. The settings are described on the following pages. Main Advanced BIOS Setup Utility PCI/PnP Boot Security Chipset Exit NorthBridge Chipset Configuration Memory Configuration ECC Configuration IOMMU Option Configuration Memory CLK :XXX MHz CAS latency (Tcl) :XX RAS/CAS Delay (Trcd) :X CLK Min Active RAS (Tras) :X CLK Row Precharge Time (Trp) :X CLK RAS/RAS Delay (Trrd) :X CLK Row Cycle (Trc) :X CLK Row Refresh Cycle (Trfc) :X CLK Read Write Delay (Trwt) :X CLK Read Preamble :X ns Asynchronous Latency :X ns Select Screen Select Item Enter Go to Sub Screen F1 General Help F10 Save and Exit ESC Exit Feature Option NorthBridge Chipset Configuration Memory CLK Read only Description It shows the clock frequency of the installed SDRAM. This controls the timing delay (in clock cycles) before SDRAM starts a read command after receiving it. When DRAM is refreshed, both rows and columns are addressed separately. This setup item allows you to determine the timing of the transition from RAS (row address strobe) to CAS (column address strobe). The less the clock cycles, the faster the DRAM performance. CAS Latency (Tcl) Read only RAS/CAS Delay (Trcd) Read only 70 http://www. TYAN. com Feature Option NorthBridge Chipset Configuration Description This setting allows you to select the number of clock cycles allotted for the RAS pulse width, according to DRAM specifications. This item controls the number of cycles for Row Address Strobe (RAS) to be allowed to precharge. If insufficient time is allowed for the RAS to accumulate its chage before DRAM refresh, refresh may be incomplete and DRAM may fail to retain data. This item applies only when synchronous DRAM is installed in the system. This is not a DRAM-specified timing parameter, but must be considered due to routing latencies on the clock forwarded bus. It is counted from the first address bus slot that was not associated with part of the read burst. The time prior to the maxread DQS-return when the DQS receiver should be turned on. The controller needs to know when to enable its DQS receiver in anticipation of the DRAM DQS driver turning on for a read. The controller will disable its DQS receiver until the read preamble time and then enable its DQS receiver while the DRAM asserts DQS. This filed should be loaded with a 4-bit value equal to the maximum asynchronous latency in the DRAM read round-trip loop. Min Active RAS (Tras) Read only Row Precharge Time (Trp) Read only RAS/RAS Delay (Trrd) Row Cycle (Trc) Row Refresh Cycle (Trfc) Read Write Delay (Trwt) Read only Read only Read only Read only Read Preamble Read only Asynchronous Latency Read only 71 http://www. TYAN. com 3. 9. 1. 1 ­ Memory Configuration Sub-Menu This menu has options for memory speed & latency. Use the Plus and Minus (+/-) keys to change the value of the selected option. Main Advanced BIOS Setup Utility PCI/PnP Boot Security Chipset Exit Memory Configuration Memclock Mode User Config Mode Bank Interleaving Burst Length Enable Clock to All DIMMs HardWare Memory Hole [Auto] [Auto] [Auto] [4 Beats] [Disabled] [Disabled] MEMCLK can be set by the code using AUTO, or if you use LIMIT, you can set one of the standard values. [. . . ] This shift the processor over and down, guiding into the board and locking it into place. 92 http://www. TYAN. com Technical Support If a problem arises with your system, you should first turn to your dealer for direct support. Your system has most likely been configured or designed by them and they should have the best idea of what hardware and software your system contains. Furthermore, if you purchased your system from a dealer near you, take the system to them directly to have it serviced instead of attempting to do so yourself (which can have expensive consequences). [. . . ]